<HTML>
<HEAD>
<TITLE>ECE 232 - Spring 2002</TITLE>
</HEAD>
<BODY background="my_background.gif">

<! -- This is a comment line -- </!>
<CENTER>
<H3> ECE 232- Project #3 </H3>
<P>
<B> Deadline: May 14, in class. </B>
<P>
Reminder: <B> Final exam </B> is scheduled for Wednesday, May 22 at 4:00pm,
at GSMN 64. 

</CENTER>
<P>
<ol>
<LI> 
<B> Combine </B> the Datapath designed in Project 1 and the FSM controller, designed
in Project 2, to create a simplified version of multicycle MIPS Processor.
<P>
<LI> 
<B> Simulate </B> the entire processor for all instructions that your datapath suports. Remember that now the only inputs to your design are IR and MD registers, and the control signals are internal. Show the content of the registers in the register file as a proof of the correctness of your design.
<P>
<LI> Prepare a <B> Final Report </B>; the report should be a self-contained document describing the entire design, and should include the following:
<ol>
  <li> Short introduction describing the processor and the instructions
	it supports. 
  <li> Top level diagram of the design; schematics and/or VHDL description
	of all its components; and the FSM diagram of the controller.
  <li> Simulation results; make sure to annotate the simulation waveforms
	showing that your machine works correctly. In particular point to the
	control signal set at the right cycles and the contents of register
	file and the ALU result.
  <li> Include a floppy with your vhdl and all design and simulation files.
	Name your top level design as MIPS_your-name.ext (ext = gdf, scm, or vhd,
	depending on the style of your design), and the top level waveform 
	with your stimulus inputs as MIPS_your-name.scf (? for waveform  	schematic).
	We will randomly check if the top level design compiles and simulates
	correctly. If it does not, or the files do not match, you loose points.
</ol>
</OL>
Good luck!
</BODY>
</HTML>


